The present invention relates to a pulse interpolator, which can correctly operate even when more than two input instruction pulses are applied within a single interpolation cycle.
Pulse interpolators are utilized in, for instance, numerical control (N.C.) systems, graph plotters, and/or machines for automatic drawing.
A prior pulse interpolator operated on the principle of D.D.A. (Digital Differential Analyzer), which has a first or integrand register (IR), a second or reminder register (RR), and an adder. Every time an input instruction pulse is applied to the D.D.A. system the content of the register (RR) and the content of the register (IR) are added in said adder, and the sum is stored in the register (RR) again. If the register (RR) overflows in the addition, the overflow pulse operates as an interpolation pulse. Therefore, a prior D.D.A. system has the disadvantage that it operates incorrectly if the duration between each input instruction pulses is shorter than the time required for each interpolation calculation (addition). In that case, an input instruction pulse will be lost and an interpolation pulse to be generated by the lost input instruction pulse will also be lost. The duration between each input instruction pulses is not uniform but changes. Particularly in the case of a screw cutting N.C.
A digital element of higher speed operation would solve the above problem, but high speed digital elements are very expensive. Further, if the duration between each input instruction pulses is designed long, the accuracy of the product of the N.C. would be poor.